Oversampling circuit and digital/analog converter

ABSTRACT

It is object to provide an oversampling circuit and a digital to analog converter capable of realizing a smaller circuit and reducing a cost of parts. The oversampling circuit comprises multiplying section  1 , four data holding sections  2 - 1  through  2 - 4 , four data selectors  3 - 1  through  3 - 4 , an adding section  4 , and two integrating circuits  5 - 1  and  5 - 2 . Input data is multiplied by four multiplicators by the multiplying section  1 , and four multiplication results held, as one set, in the data holding sections. The data selectors read out the data held in the four data holding sections in a predetermined order and generate step function data. The adding section adds the values of four step functions outputted from the respective data selectors, and then digital integrating operations corresponding to the sum are carried out by means of two integrating circuits.

TECHNICAL FIELD

[0001] The present invention relates to an over sampling circuit forinterpolating input data discretely and a digital-to-analog converter towhich the oversampling circuit is applied. In this specification, it isassumed that a case where function values have finite values except zeroin a local region and become zero in regions different from the regionis called a “local support.”

BACKGROUND ART

[0002] A recent digital audio apparatus, for example, a CD (CompactDisk) player, uses a D/A (digital-to-analog) converter to which anover-sampling technique is applied to obtain a continuous analog audiosignal from discrete music data (digital data). Such a D/A convertergenerally uses a digital filter to raise a pseudo sampling frequency byinterpolating input digital data, and outputs smooth analog audiosignals by passing each interpolation value through a low-pass filterafter generating a staircase signal waveform with each interpolationvalue held by the sample holding circuit.

[0003] A data interpolation system disclosed in WO99/38090 is well knownas a method of interpolating data into discrete digital data. In thisdata interpolation system, differentiation can be performed only once inthe whole range, and a sampling function is used such that two samplingpoints each before and after an interpolation position, that is, a totalof four sampling points, can be considered. Since the sampling functionhas values of a local support unlike the sinc function defined by sin(πft)/(πft) where f indicates a sampling frequency, there is a meritthat no truncation errors occur although only four pieces of digitaldata are used in the interpolating operation.

[0004] Generally, oversampling is performed by using a digital filter inwhich the waveform data of the above mentioned sampling function is setto a tap coefficient of an FIR (finite impulse response) filter.

[0005] If the oversampling technology of performing an interpolatingoperation for discrete digital data using the above mentioned digitalfilter, a low pass filter having a moderate attenuation characteristiccan be used. Therefore, the phase characteristic with a low pass filtercan approach a linear phase characteristic, and the sampling aliasingnoise can be reduced. These effects are more outstanding with a higheroversampling frequency. However, if the sampling frequency becomeshigher, the number of taps of the digital filter is also increased. As aresult, there arises the problem of a larger circuit. In addition, theperformance of the delay circuit or multiplier comprises the digitalfilter is also sped up. Therefore, it is necessary to use expensiveparts appropriate for the quick performance, thereby increasing the costof the required parts. Especially, when the oversampling process isperformed using a digital filter, an actual value of a sampling functionis used as a tap coefficient. Therefore, the configuration of amultiplier is complicated, and the cost of the parts furthermoreincreases.

[0006] Moreover, although a digital-to-analog converter can beconfigured by connecting a low pass filter after the oversamplingcircuit, the above mentioned various problems with the conventionaloversampling circuit have also occurred with the digital-to-analogconverter configured using the circuit.

BRIEF SUMMARY OF THE INVENTION

[0007] The present invention has been achieved to solve the abovementioned problems, and aims at providing an oversampling circuit and adigital-to-analog converter having a smaller circuit at a lower cost ofparts.

[0008] In the oversampling circuit according to the present invention, amultiplying unit performs a plurality of multiplying processes usingplural multiplicators on a plurality of digital data input atpredetermined intervals, and using the plurality of multiplicationresult, step function is generated corresponding to each inputteddigital data. By performing digital integration plural times on theaddition results obtained by addition unit adding up values of the stepfunction corresponding to each digital data, digital data whose valueschange stepwise is output along a smooth curve. Thus, the values of stepfunction corresponding to sequentially input plural pieces of digitaldata are added up, and then the digital integration is performed on theaddition result. As a result, output data whose values smoothly changecan be obtained. Therefore, when an oversampling frequency is high, itis necessary only to speed up the digital integration, thereby avoidingthe conventional complicated configuration, that is, simplifying theconfiguration, and reducing the cost of parts.

[0009] Each of the multiplicators used in the multiplying processes bythe multiplying unit is desired to correspond to each of the values ofstep functions obtained by differentiating plural times piecewisepolynomials for a predetermined sampling function configured by thepiecewise polynomials. That is, by integrating plural times the abovementioned step function, a waveform corresponding to the predeterminedsampling function can be obtained. Therefore, a convolution operationusing a sampling function can be equivalently realized by generating astep function. As a result, the contents of the entire process can besimplified, and the number of processes required oversampling can besuccessfully reduced.

[0010] In addition, the above mentioned step function is desired toequally set the positive and negative areas. Thus, the divergence ofintegration results of the integrating unit can be prevented.

[0011] Furthermore, it is desirable that the above mentioned samplingfunction has a value of local support with the whole rangedifferentiable only once. It is assumed that a natural phenomenon can beapproximated if the whole range is differentiable only once. By settinga smaller number of times of differentiation, the times of the digitalintegration performed by the integrating unit can be reduced, therebysuccessfully simplifying the configuration.

[0012] It is further desirable that the above mentioned step functioncontains an area of eight piecewise sections in equal width weighted by−1, +3, +5, −7, −7, +5, +3, and −1 in a predetermined rangecorresponding to five pieces of digital data arranged at equalintervals, and that the eight weight coefficients are set as therespective multiplicators of multiplying unit. Since simple weightcoefficients represented by integers can be used as the multiplicatorsin the multiplying unit, the multiplying process can be simplified.

[0013] Especially, it is desirable that a multiplying process performedin the multiplying unit is represented by adding digital data to anoperation result of the exponentiation of 2 by a bit shift. Since themultiplying process can be replaced with a bit shift process and anadding operation, the configuration can be simplified and the processcan be sped up by simplifying the contents of the processes.

[0014] It is also desirable that the times of the digital integration istwo, and a data whose value changes like a quadric function is outputfrom the integrating unit. For smooth interpolating plural pieces ofdiscrete data, it is necessary at least to change a value like a quadricfunction. Since it can be realized only by setting the number of timesof the digital integration to 2, the configuration of the integratingunit can be simplified.

[0015] Furthermore, the digital integration performed by the integratingunit is a process of accumulating input data, and it is desirable thatthe process is repeated n times in a period of inputting digital data.Thus, the operation of accumulating data can be realized only by addingthe input data. Therefore, the configuration of the integrating unit canbe simplified, and the process can be easily and more quickly repeated.As a result, the value of the multiple n of the oversampling can be setto a large value without complicating the configuration and largelyincreasing the cost of parts.

[0016] In addition, the digital-to-analog converter can be configuredonly by providing voltage generation unit and smoothing unit at thestage after the above mentioned oversampling circuit. Accordingly, thedigital-to-analog converter according to the present invention can berealized with a simplified configuration and reduced cost of parts.Furthermore, the above mentioned oversampling circuit can easily set ahigh oversampling frequency without complicating the configuration orlargely increasing the cost of parts. As a result, the distortion of theoutput waveform of the digital-to-analog converter to which theoversampling circuit is applied can be minimized.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1 is a diagram showing a sampling function used in aninterpolating operation in the oversampling circuit according to anembodiment;

[0018]FIG. 2 is a diagram showing a relationship between the samplingvalues with an interpolation values;

[0019]FIG. 3 is a diagram showing a waveform obtained by differentiatingonce the sampling function shown in FIG. 1;

[0020]FIG. 4 is a diagram showing a the waveform obtained by furtherdifferentiating the polygonal line function shown in FIG. 3;

[0021]FIG. 5 is a diagram showing a the configuration of an oversamplingcircuit of an embodiment;

[0022]FIG. 6 is a block diagram showing a detailed configuration of anintegrating circuit included in the oversampling circuit shown in FIG.5;

[0023]FIGS. 7A through 7L are charts showing the operation timings ofthe oversampling circuit of an embodiment;

[0024]FIGS. 8A and 8B are diagrams showing detailed data output from theintegrating circuits;

[0025]FIG. 9 is a diagram showing a detailed configuration of themultiplying section; and

[0026]FIG. 10 is a diagram showing a configuration of the D/A converterto which the oversampling circuit shown in FIG. 5 is applied.

BEST MODE FOR CARRYING OUT THE INVENTION

[0027] An embodiment of the oversampling circuit according to thepresent invention is described below in detail by referring to theattached drawings. FIG. 1 shows a sampling function used in aninterpolating operation in the oversampling circuit according to thepresent embodiment. The sampling function H(t) is disclosed byWO99/38090, and represented by the following expressions.$\begin{matrix}\begin{matrix}{{\left( {{- t^{2}} - {4t} - 4} \right)/4};} & {{- 2} \leq t < {{- 3}/2}} \\{{\left( {{3t^{2}} + {8t} + 5} \right)/4};} & {{{- 3}/2} \leq t < {- 1}} \\{{\left( {{5t^{2}} + {12t} + 7} \right)/4};} & {{- 1} \leq t < {{- 1}/2}} \\{{\left( {{{- 7}t^{2}} + 4} \right)/4};} & {{{- 1}/2} \leq t < 0} \\{{\left( {{{- 7}t^{2}} + 4} \right)/4};} & {0 \leq t < {1/2}} \\{{\left( {{5t^{2}} - {12t} + 7} \right)/4};} & {{1/2} \leq t < 1} \\{{\left( {{3t^{2}} - {8t} + 5} \right)/4};} & {1 \leq t < {3/2}} \\{{\left( {{- t^{2}} + {4t} - 4} \right)/4};} & {{3/2} \leq t \leq 2}\end{matrix} & (1)\end{matrix}$

[0028] where t=0, ±1, ±2 indicates the sampling position. The samplingfunction H(t) shown in FIG. 1 can be differentiated only once in thewhole range, and is a function of local support converging into 0 withthe sampling position t=±2. By performing an overlapping process usingthe sampling function H(t) based on each sampling value, theinterpolating process can be performed using a function differentiableonly once in the sampling values.

[0029]FIG. 2 shows the relationship between the sampling values and theinterpolation values. As shown in FIG. 2, assume that four samplingpositions are t1, t2, t3, and t4, and the distance between two adjacentsampling positions is 1. The interpolation value y corresponding to theinterpolation position t0 between the sampling positions t2 and t3 isobtained by the following equation. $\begin{matrix}\begin{matrix}{y = \quad {{Y\quad {({t1}) \cdot {H\left( {1 + a} \right)}}} + {Y\quad {({t2}) \cdot H}\quad (a)} +}} \\{\quad {{{{Y({t3})} \cdot H}\quad \left( {1 - a} \right)} + {Y\quad {({t4}) \cdot {H\left( {2 - a} \right)}}}}}\end{matrix} & (2)\end{matrix}$

[0030] where Y(t) indicates each sampling value at the sampling positiont. Each of 1+a, a, 1−a, and 2−a indicates the distance between theinterpolation position t0 and each of the sampling positions t1 throught4.

[0031] As described above, by performing a convolution operation bycomputing the value of the sampling function H(t) corresponding to eachsampling value, an interpolation value of sampling values can beobtained theoretically. However, the sampling function shown in FIG. 1is a quadric piecewise polynomial differentiable only once in the wholerange. Using this feature, the interpolation value can be obtained inanother equivalent process procedure.

[0032]FIG. 3 shows a waveform obtained by differentiating once thesampling function shown in FIG. 1. The sampling function H(t) shown inFIG. 1 is a quadric piecewise polynomial differentiable once in theentire range. Therefore, by performing the differentiation once, apolygonal line function formed by the waveform of a continuous polygonalline as shown in FIG. 3 can be obtained.

[0033]FIG. 4 shows the waveform obtained by further differentiating thepolygonal line function shown in FIG. 3. However, the polygonal linewaveform contains a plurality of corner points, and the differentiationcannot be performed in the whole range. Therefore, the differentiationis performed on the linear portion between two adjacent corner points.By differentiating the polygonal line waveform shown in FIG. 3, the stepfunction formed by the stepwise waveform as shown in FIG. 4 can beobtained.

[0034] Thus, the above mentioned sampling function H(t) is oncedifferentiated in the entire range to obtain a polygonal line function.By further differentiating each of the linear portions of the polygonalline function, a step function can be obtained. Therefore, in thereverse order, by generating the step function shown in FIG. 4, andintegrating it twice, the sampling function H(t) shown in FIG. 1 can beobtained.

[0035] In the step function shown in FIG. 4, the positive and negativeareas are set equal to each other, and the sum of the areas equals 0.That is, by integrating such a step function plural times, a samplingfunction of local support, as shown in FIG. 1, whose differentiabilityin the whole range is guaranteed can be obtained.

[0036] In computing the interpolation value in the convolution operationshown by the equation (2), the value of the sampling function H(t) ismultiplied by each sampling value. If the sampling function H(t) isobtained by integrating twice the step function shown in FIG. 4, thevalue of the sampling function obtained in the integrating process ismultiplied by each sampling value, or equivalently, when a step functionbefore the integration processing is generated, an interpolation valuecan be obtained by generating a step function by multiplication by eachsampling value, and performing twice the integrating process on theresult obtained in the convolution operation using the step function.The oversampling circuit according to the present embodiment obtains aninterpolation value as described above. This process is described belowin detail.

[0037]FIG. 5 shows the configuration of the oversampling circuitaccording to the present embodiment. The oversampling circuit shown inFIG. 5 comprises a multiplying section 1, four data holding sections2-1, 2-2, 2-3, and 2-4, four data selectors 3-1, 3-2, 3-3, and 3-4, anadding section 4, and two integrating sections 5-1, 5-2.

[0038] The multiplying section 1 outputs a result of multiplyingdiscrete digital data sequentially input at predetermined time intervalsby a multiplicator corresponding to each value of the step functionshown in FIG. 4. Each value of the step functions shown in FIG. 4 can beobtained by twice differentiating each piecewise polynomial of the abovementioned equation (1) as follows. −1 ;−2 ≦ t < {fraction (−3/2)} +3;{fraction (−3/2)} ≦ t < −1 +5 ;−1 ≦ t < {fraction (−1/2)} −7 ;{fraction(−1/2)} ≦ t < 0 −7 ;0 ≦ t < ½ +5 ;½ ≦ t < 1 +3 ;1 ≦ t < {fraction (3/2)}−1 ;{fraction (3/2)} ≦ t ≦ 2

[0039] Therefore, the multiplying section 1 multiplies the input data Dby four types of the value corresponding to the above mentioned stepfunctions as multiplicators (−1, +3, +5, and −7), when the data D isinput, and concurrently outputs a set of four-piece data, that is, −D,+3D, +5D, and -7D.

[0040] The data holding sections 2-1 through 2-4 cyclically fetch a setof four-piece data output from the multiplying section 1, and hold thedata until the next fetching timing. For example, a set of four-piecedata output from the multiplying section 1 corresponding to the firstinput data is fetched and held in the data holding section 2-1, and aset of four-piece data output from the multiplying section 1corresponding to the second input data is fetched and held in the dataholding section 2-2. Similarly, each set of four-piece data output fromthe multiplying section 1 corresponding to the third and fourth inputdata is fetched and held in the data holding section 2-3, and 2-4,respectively. When a cycle of the data holding operation is completed inthe data holding sections 2-1 through 2-4, then the next output datafrom the multiplying section 1 corresponding to the fifth input data isfetched and held by the data holding section 2-1 which has first heldthe data. Thus, sets of four-piece data sequentially output from themultiplying section 1 corresponding to the input data are cyclicallyheld by the data holding sections 2-1, etc.

[0041] The data selectors 3-1 through 3-4 output data whose valueschange stepwise corresponding to a step function by sequentially readingfour pieces of data held in the one-to-one corresponding to the dataholding sections 2-1 through 2-4 in a predetermined order. Practically,for example, when four pieces of data (−D, +3D, +5D, and −7D) obtainedby multiplying the data D by the above mentioned four types ofmultiplicators are held in the data holding section 2-1, the dataselector 3-1 cyclically reads the held digital data in the order of −D,+3, +5D, −7D, −7D, +5D, +3D, and −D at predetermined time intervals,thereby outputting the data of step functions having a valueproportional to the input data D.

[0042] The adding section 4 adds up digitally the values of the stepfunctions output from four data selectors 3-1 through 3-4. The twoserially connected integrating circuits 5-1 and 5-2 perform twointegrating processes on the data output from adding section 4. Alinearly changing data (like a linear function) is output from theintegrating circuit 5-1 at the first stage, and a data changing like aquadric function is output from the integrating circuit 5-2 at thesubsequent stage.

[0043]FIG. 6 shows the detailed configuration of the integratingcircuits 5-1 and 5-2. The integrating circuit 5-1 at the preceding stagecomprises two D flip-flops (D-FF) 51 a and 51 c and an adder (ADD) 51 b.The adder 51 b has two input terminals. Data output from the addingsection 4 and temporarily held in the D flip-flop 51 a is input into oneinput terminal, and data output from the adder 51 b itself andtemporarily held in the D flip-flop 51 c is input into the other inputterminal. Each of the D flip-flops 51 a and 51 c holds the datasynchronous with the clock signal CLK2 for an integrating operation. Theclock signal CLK2 corresponds to the oversampling frequency, and is setto the frequency n times as high as the frequency of the clock signalCLK synchronized with input timing of the input data. Therefore, whenthe data output from the adding section 4 is input into the integratingcircuit 5-1 with the above mentioned configuration, a digitalintegrating operation for accumulating the input data is performed insynchronization with the clock signal CLK2.

[0044] The integrating circuit 5-2 at the subsequent stage has thebasically the same configuration as the above mentioned integratingcircuit 5-1 at the preceding stage, and comprises two D flip-flops(D-FF) 52 a and 52 c and an adder (ADD) 52 b. When data output from theintegrating circuit 5-1 at the preceding stage is input into theintegrating circuit 5-2 with the above mentioned configuration, adigital integrating operation for accumulating the input data isperformed in synchronization with the clock signal CLK2.

[0045] Since the value of the step function output from the abovementioned data selector 3-1 is proportional to the value of the digitaldata input to the multiplying section 1 at predetermined timing, thedata output from the subsequent integrating circuits 5-2 by performingtwice the integrating process on the value of the step function by thetwo integrating circuits 5-1 and 5-2 include the data corresponding tothe multiplication result of the sampling function shown in FIG. 1 bythe input data. Also, the adding section 4 adds up the values of thestep functions output from data selectors 3-1 through 3-4. This can beequivalently performed by the convolution process using a step functionas shown in FIG. 1, paying attention to an output data from theintegrating circuit 5-2 at the subsequent stage.

[0046] Therefore, in the case of inputting digital data into theoversampling circuit according to the present embodiment at apredetermined time intervals, the outputting timing of data of the stepfunction from each data selector is shifted corresponding to the inputinterval, and the step functions respectively generated are added up,then the adding results are performed the integrating operation twice,thereby obtaining digital data whose values change stepwise along thecurve smoothly connecting digital data input at predetermined intervals.

[0047] The above mentioned multiplying section 1 corresponds tomultiplying unit, the combinations of the data holding section 2-1, orthe like, and the data selector 3-1, or the like correspond to the stepfunction generation unit, the adding section 4 corresponds to theaddition unit, and the integrating sections 5-1 and 5-2 correspond tointegrating unit, respectively.

[0048]FIGS. 7A to 7L are charts showing the operation timings of theoversampling circuit in this embodiment. As shown in FIG. 7A, if thedigital data D₁, D₂, D₃, . . . are input at a constant time interval,each of the data holding sections 2-1 through 2-4 holds four datacorresponding to these digital data D₁, D₂, D₃, . . . cyclically. Morespecifically, the data holding section 2-1 fetches four data −D₁, +3D₁,+5D₁, −7D₁ output from the multiplying section 1 corresponding to thefirst input data D₁, and holds the data till the input digital data iscirculated (or till four data corresponding to a fifth input data D₅(−D₅, +3D₅, +5D₅, −7D₅) is input) (FIG. 7B). The data selector 3-1 readsout four data corresponding to the first input data D₁ in predeterminedorder, and generates a step function having a value proportional to theinput data D₁ (FIG. 7C).

[0049] Similarly, the data holding section 2-2 fetches four data −D₂,+3D₂, +5D₂, −7D₂ output from multiplying section 1 corresponding to thesecond input data D₂, and holds the data till the input digital data iscirculated (or till four data corresponding to a sixth input data D₆ isinput) (FIG. 7D). The data selector 3-2 reads out four datacorresponding to the second input data D₂ in predetermined order, andgenerates a step function having a value proportional to the input dataD₂ (FIG. 7E).

[0050] The data holding section 2-3 fetches four data −D₃, +3D₃, +5D₃,−7D₃ output from multiplying section 1 corresponding to the third inputdata D₃, and holds the data till the input digital data is circulated(or till four data corresponding to a seventh input data D₇ is input)(FIG. 7F). The data selector 3-3 reads out four data corresponding tothe third input data D₃ in predetermined order, and generates a stepfunction having a value proportional to the input data D₃ (FIG. 7G).

[0051] The data holding section 2-4 fetches four data −D₄, +3D₄, +5D₄,−7D₄ output from multiplying section 1 corresponding to the fourth inputdata D₄, and holds the data till the input digital data is circulated(or till four data corresponding to a eighth input data D₈ is input)(FIG. 7H). The data selector 3-4 reads out four data corresponding tothe fourth input data D₄ in predetermined order, and generates a stepfunction having a value proportional to the input data D₄ (FIG. 7I).

[0052] The adding section 4 adds values of step functions output fromeach of four data selectors 3-1 through 3-4 in this way. By the way, thestep function generated by each of the data selectors 3-1 through 3-4 asshown in FIG. 4 is a function of a local support having eight piecewisesections divided at every 0.5 from a region of the sample position t=−2to +2 in which the sampling function of FIG. 1 has finite values. Forexample, a first piecewise section, a second piecewise section, . . . ,and an eighth piecewise section are defined in a direction from thesample position t=−2 to +2.

[0053] More specifically, the adding section 4 at first adds a value(+3D₁) corresponding to the seventh piecewise section that is outputfrom the data selector 3-1, a value (−7D₂) corresponding to the fifthpiecewise section that is output from the data selector 3-2, a value(+5D₃) corresponding to the third piecewise section that is output fromthe data selector 3-3, and a value (−D₄) corresponding to the firstpiecewise section that is output from the data selector 3-4 to output aresult of addition (+3D₁ −7D₂ +5D₃ −D₄).

[0054] Then, the adding section 4 adds a value (−D₁) corresponding tothe eighth piecewise section that is output from the data selector 3-1,a value (+5D₂) corresponding to the sixth piecewise section that isoutput from the data selector 3-2, a value (−7D₃) corresponding to thefourth piecewise section that is output from the data selector 3-3, anda value (+3D₄) corresponding to the second piecewise section that isoutput from the data selector 3-4 to output a result of addition(−D₁+5D₂−7D₃+3D₄).

[0055] Thus, when addition results are sequentially output in the formof steps from the adding section 4 (FIG. 7J), the integrating circuit5-1 at the preceding stage outputs plural pieces of data whose valueschange in the form of the polygonal line by integrating the data (FIG.7K). The integrating circuit 5-2 at the subsequent stage furtherintegrates the data whose values changes in the form of the polygonalline, and outputs plural pieces of data whose values change along asmooth curve differentiable only once between the input data D₂ and D₃(FIG. 7L).

[0056]FIGS. 8A and 8B show the details of the data output from the twointegrating circuits 5-1 and 5-2. For example, the frequency of theclock signal CLK2 for an integrating operation input into each of theintegrating circuits 5-1 and 5-2 is set to 20 times as high as thesampling frequency (frequency of the clock signal CLK) of the inputdata. As shown in FIG. 8A, the plural pieces of data output from theintegrating circuit 5-1 at the preceding stage have values changing likea linear function. As shown in FIG. 8B, the plural pieces of data outputfrom the integrating circuit 5-2 at the subsequent stage have valueschanging like a quadric function.

[0057] In each of the integrating circuits 5-1 and 5-2 whoseconfigurations are shown in FIG. 6, a digital integrating process isperformed by simply accumulating input data. Therefore, since the valueof the data output therefrom becomes larger depending on the multiple ofthe oversampling, it is necessary to provide a division circuit at theoutput stage of each of the integrating circuits 5-1 and 5-2 in order tomake the values of input output data coincident. For example, in theexample shown in FIG. 8, since the value of the output data is 20 timesas large as the input data, a division circuit having a divisor of 20 isprovided at the end of each of the integrating circuits 5-1 and 5-2.However, when a multiple of the oversampling is set to a value of thepower of 2 (for example, 2, 4, 8, 16, . . .), a dividing process can beperformed on output data by bit-shifting the output data of each of theintegrating circuits 5-1 and 5-2 toward lower bits, thereby omitting theabove mentioned division circuit. For example, when the multiple of theoversampling is set to 16, the output data from each of the integratingcircuits 5-1 and 5-2 can be shifted by 5 bits toward lower bits.Therefore, the wiring at the output terminal of each circuit can beshifted by 5 bits in advance.

[0058] Thus, the oversampling circuit according to the presentembodiment holds the four multiplication results as a unit correspondingto each input digital data in the four data holding sections 2-1 through2-4 cyclically. The data selectors 3-1 through 3-4 read out the fourheld data in predetermined order, thereby generating the step functions.Then, adding section 4 adds the values of the step function whilecorresponds to the four input data. And then, by performing a digitalintegrating process twice by the two integrating circuits 5-1 and 5-2 onthe data output from the adding section 4, an oversampling process canbe performed for increasing in a pseudo manner a sampling frequency ntimes as high as the frequency of each piece of the input digital data.

[0059] Especially, the oversampling circuit according to the presentembodiment sets how many times the sampling frequency of the input datathe oversampling frequency is to be set depends only on the frequency ofthe clock signal CLK2 input into the two integrating circuits 5-1 and5-2. That is, the multiple of the oversampling can be set large only byconfiguring the two integrating circuits 5-1 and 5-2 using high-speedparts. Therefore, unlike the conventional method of performing theoversampling process using a digital filter, the entire circuit is notlarge although the frequency of the oversampling is set higher, therebyminimizing the increase of the cost of parts. Furthermore, the contentsof the operations can be simplified by using the four multiplicatorsrepresented by integers in the multiplying process by the multiplyingsection 1, thereby simplifying the configuration of the multiplyingsection, and reducing the cost of parts.

[0060] Furthermore, for example, when an oversampling process isperformed to obtain a pseudo frequency n times as high as the samplingfrequency (for examples, 1024 times), it has been necessary in theconventional method to have the operation speed of the parts as high asthe pseudo frequency. However, according to the oversampling circuit ofthe present embodiment, except the two integrating circuits, it isnecessary to operate the each data holding sections and each dataselector, etc. at the sampling frequency or the frequency twice as highas the sampling frequency, thereby considerably reducing the operationspeed of each part.

[0061]FIG. 9 shows the detailed configuration of the multiplying section1 shown in FIG. 5. The multiplying section 1 shown in FIG. 9 comprisestwo inverters 10 and 11 for inverting the logic of each bit of the inputdata and outputting the result, a multiplier 12 for multiplying by themultiplicator of 2, a multiplier 13 for multiplying by the multiplicatorof 4, a multiplier 14 for multiplying by the multiplicator of 8, andfour adders 15, 16, 17, and 18.

[0062] For example, when data D₁ is input into the multiplying section 1which has the configuration as mentioned above, the inverter 10 outputsthe data obtained by inverting the logic of each bit of the input dataD₁, the adder 15 adds 1 to the lowest bit of each piece of the outputdata, thereby obtaining the complement of the input data D₁. Thisequivalently shows the value (−D₁) obtained by multiplying the inputdata D₁ by −1. Furthermore, the multiplier 12 outputs a value (+2D₁) twotimes as large as the value of the input data D₁, and the adder 16 addsthe original input data D₁, to the data, thereby obtaining the value(+3D₁) three times as large as the input data D₁. Similarly, themultiplier 13 outputs a value (+4D₁) four times as large as the inputdata D₁, and the adder 17 adds the value to the original input data D₁,thereby obtaining a value (+5D₁) five times as large as the input dataD₁. Additionally, the multiplier 14 outputs a value (+8D₁) eight timesas large as the input data D₁, the inverter 11 inverts the logic of eachbit of the output data, and the adder 18 adds the original input data D₁to the inverted data. The adder 18 has a valid carry terminal C, andadds 1 to the lowest bit of the output data of the inverter 11, therebyobtaining the complement of the output data of the inverter 11.Therefore, a value (−7D₁) −7 times as large as the input data D₁ can beobtained by adding the original input data D₁ to the value (−8D₁) −8times as large as the input data D₁, by means of the adder 18.

[0063] Since the multiplicators are power of 2, the above mentionedthree multipliers 12, 13, and 14 can perform the multiplying processonly by performing bit shifting operation. Thus, by combining themultiplying process of the power of 2 by the bit shift with the addingprocess, the multiplying process is performed by four multiplicators,thereby simplifying the configuration.

[0064] A D/A converter can be configured with smaller number of parts byadding a low pass filter, etc. at the subsequent stage of the abovementioned oversampling circuit. FIG. 10 shows the configuration of theD/A converter. The D/A converter has the configuration obtained byadding a D/A converter 6 and a low pass filter (LPF) 7 at the subsequentstage of the oversampling circuit shown in FIG. 5. The D/A converter 6corresponds to the voltage generation unit, and the low pass filter 7corresponds to the smoothing unit.

[0065] The D/A converter 6 generates an analog voltage corresponding tothe stepwise digital data output by the integration circuit 5-2 at thesubsequent stage. The D/A converter 6 generates a constant analogvoltage proportional to the value of the input digital data, and thevoltage value at the output terminal of the D/A converter 6 also changesstepwise. The low pass filter 7 smoothes the output voltage of the D/Aconverter 6, and outputs a smoothly changing analog signal.

[0066] Since the D/A converter shown in FIG. 10 uses the oversamplingcircuit shown in FIG. 5, the configuration can be simplified and thecost of parts can be reduced. Although an output waveform is obtainedwith less distortion and the oversampling frequency set high, theconfiguration is not complicated with reduced cost.

[0067] The present invention is not limited to the above mentionedembodiment, and various types of embodiments can be set within the scopeof the gist of the present invention. For example, according to theabove mentioned embodiment, a sampling function is defined as a functionof local support differentiable only once in the whole range, but thetimes of differentiation can be set to a value equal to or larger than2. In this case, the number of integrating circuits is to match thenumber of times of differentiation.

[0068] The sampling function of this embodiment converges to zero att=±2, as shown in FIG. 1, but may converge to zero at t=±3 or beyond.For example, in a case of the sampling function converging to zero att=±3, six data holding sections and six data selectors may be containedin the oversampling circuit shown in FIG. 5, to interpolate for the sixdigital data.

[0069] Furthermore, it is not limited to the interpolating process usinga sampling function of local support, but using a sampling functiondifferentiable finite times having a predetermined value in the rangefrom −∞ to +∞, an interpolation process may be performed only for pluraldigital data corresponding to finite sample position. For example,assuming that the sampling function is defined by a quadric piecewisepolynomial, a predetermined step function can be obtained by twicedifferentiating each piecewise polynomial. Therefore, a convolutionoperation is performed using this step function, and an operation resultis integrated twice, thereby performing an oversampling process.

INDUSTRIAL APPLICABILITY

[0070] As described above, according to the present invention, aplurality of multiplying processes are performed using pluralmultiplicators on a plurality of digital data input at predeterminedintervals. Using the plurality of multiplication result, the stepfunctions are generated corresponding to each input digital data. Byperforming digital integration plural times on the addition resultsobtained by adding up values of the step function corresponding to eachinput digital data, digital data whose values change stepwise is outputalong a smooth curve. Therefore, when an oversampling frequency is high,it is necessary only to speed up the digital integration, therebyavoiding the conventional complicated configuration, that is,simplifying the configuration, and reducing the cost of parts.

1. An oversampling circuit, characterized by comprising: a multiplyingunit for performing a plurality of multiplying process using pluralmultiplicators on plural pieces of digital data inputted at apredetermined intervals; a plurality of step function generation unitfor generating step functions corresponding to each of the plural piecesof digital data using plural of multiplication result obtained by themultiplying unit synchronized with an input timing of each of the pluralpieces of digital data; an addition unit for performing a process ofadding up values of the step functions generated by the plurality ofstep function generation unit; and an integrating unit for performing adigital integrating process plural times on output data from theaddition unit.
 2. The oversampling circuit according to claim 1,characterized in that each of the multiplicators used in the multiplyingprocesses by the multiplying unit corresponds to each of the values ofstep functions obtained by differentiating plural times piecewisepolynomials for a predetermined sampling function configured by thepiecewise polynomials.
 3. The oversampling circuit according to claim 2,wherein said step function comprises a positive region and a negativeregion set to have an equal area.
 4. The oversampling circuit accordingto claim 3, wherein said sampling function is differentiable only onceover the whole range and has values of local support.
 5. Theoversampling circuit according to claim 2, characterized in that saidstep function consists of eight piecewise sections in equal width with aweight of −1, +3, +5, −7, −7, +5, +3, and −1 in a predetermined rangecorresponding to said five digital data arranged at an equal interval,and that the eight weight coefficients are set as the multiplicators ofsaid multiplying unit.
 6. The oversampling circuit according to claim 5,characterized in that a multiplying process performed by saidmultiplying unit is realized by adding said digital data to an operationresult of an exponentiation of 2 by a bit shift.
 7. The oversamplingcircuit according to claim 1, characterized in that times of saiddigital integration is two, and data whose value changes like a quadricfunction is output from said integrating unit.
 8. The oversamplingcircuit according to claim 1, characterized in that said digitalintegration performed by said integrating unit is an operating processof accumulating input data, and n times of an oversampling process isperformed by repeatedly performing the operating process n times in oneperiod of inputting the digital data.
 9. A digital-to-analog converter,comprising at a stage subsequent to said oversampling circuit accordingto claim 1: voltage generation unit for generating an analog voltagecorresponding to a value of data output by said integrating unit; andsmoothing unit for smoothing the analog voltage generated by saidvoltage generation unit.